1. Field of the Invention
The invention relates to bypass circuits for use in digital logic circuits, and in particular to a bypass circuit for use with a clock driver input used in integrated circuits fabricated using MOS technology.
2. Description of the Prior Art
Various types of clock driver circuits using MOS technology are known in the prior art. U.S. Pat. No. 4,250,408 describes a regulated circuit for use with a digital logic circuit which includes a sensing and regulator circuit for compensating for variations in the voltage levels, typically due to process parameter variations.
Although the above-noted patent is directed to proportionally reducing the voltage range of a clock signal applied thereto to a predetermined smaller voltage range, such circuits are not directed to the relative duration of the high level and low level portions of a clock input signal. Certain types of clocking signals applied to an integrated circuit device may have a constant predetermined frequency, but for sundry reasons the duration of the high level portion of a clock cycle may not be exactly equal to the duration of the low level portion of the clock signal. Such unequal high level and low level portions of an input clock signal may result in timing inaccuracies in various circuit components which may substantially effect the operation of the device.
The circuits of the prior art are not sufficient to handle the timing inaccuracies or variations in clocking frequency which may be due to various factors external to the integrated circuit chip under consideration. Prior to the present invention a satisfactory technique for handling such clocking variations by means internal to the integrated chip itself was not available.